Pulse amplifier

ABSTRACT

Pulse amplifier for use with a capacitive load which produces output pulses having a short rise and fall time. The amplifier is basically a current-mode-switch having an emitter follower circuit uniquely connected at its output to reduce the storage effect of stray capacitance in the load circuits.

I United States Patent [151 3, Shigaki [45] Nov. 14, 1972 PULSEAMPLIFIER 3,378,701 4/ 1968 Frank ..307/246 72 In t hi aki Kan p, et 1 cm g agawa 3,469,112 9/1969 Hand 6mm. ..328/151 [73] Asslgnee:Communication Satellite Corpora- 3,506,854 4/1970 Guzak ..307/268 tion,Washington, DC. 3,527,887 9/1970 Clapp et al. ..307/268 [22] Filed: Feb24 1971 3,573,502 4/1971 Kan ..307/268 [21] Appl. No.: 118,241 PrimaryExaminer-Archie R. Borchelt Assistant Examiner-Harold A. Dixon A .K 52US. Cl. ..307/246, 307/238, 307/268, omey asper 328/66 57 ABSTRACT [51]Int. Cl. ..H03k 17/56 1 58 Field 6: Search ..328/151, 66; 307/246, 268,Pulse ampllfifl for use with a capamve 307/238 produces output pulseshaving a short rise and fall time. The amplifier is basically acurrent-mode-switch [56] References Cited having an emitter followercircuit uniquely connected at its output to reduce the storage effect ofstray UNITED STATES PATENTS capacitance in the load circuits.

2,621,263 12/1952 Scoles ..328/151 2 Claims, 2 Drawing Figures CLOCKPULSE INPUT PATENTEBnuv 151m 3,702,944

WlTH POSITIVE ENHANCEMENT FIG. 2

SEIICHIRO SHIGAKI INVENTOR ATTORNEY PULSE AMPLIFIER BACKGROUND OF THEINVENTION The subject matter of the present invention is generallyconcerned with the amplification of pulses having short rise and falltimes in applications wherein the amplified pulse must be supplied to acapacitive load. More particularly the invention includes acurrent-mode-switch having as an input a train of low amplitude pulseswhich are applied to a load having a substantial stray capacitance. Anemitter follower circuit is employed at the output of thecurrent-mode-switch to reduce the transient rise time due to the storageof energy in the stray capacitance of the load.

Digital signals which require less bandwidth than analog signals andarerelatively unaffected by the normal distortion and attenuation of thetransmission system are frequently used for long distance communication.The digital transmission of analog information is generally accomplishedthrough the steps of (l) digitally encoding the analog signal into aseries of information bits which approximate the variable amplitudeanalog signal, (2) transmitting the digital information, and (3)subsequently decoding the digital bits into a reconstructed analogsignal.

The digital encoding of analog information is facilitated by a pulsecode modulation (PCM) encoder which initially samples the analog signalat high speed and produces a series of pulse amplitude modulation (PAM)pulses having variable amplitudes which together form a discontinuousapproximation of the original signal. Each pulse in the series of pulsesis then amplified and quantized, that is compared to reference voltagesfor conversion into digital signals representative of the amplitude ofthe pulse. The stream of digital bits is transmitted to a remotereceiver where the bits are decoded into a series of PAM signals and thePAM signals are subsequently converted into a reconstructed analogsignal.

Although the transmitted digital signal may be satisfactorallyreproduced at the receiver, the recon structed analog signal will not beidentical to the original signal due to the coding function performed.

Even assuming that a perfectly square PAM pulse is possible, the systemis inherently inaccurate due to the PAM signal approximation of theanalog signal at the transmitter. In practice this inaccuracy may bemagnified by the slow rise and fall times of individual PAM pulses whichresult in distorted coding and decoding.

The PAM pulses at the transmitter are produced by a sampling circuitwhich has as one input the analog signal to be transmitted and as asecond input a train of sampling pulses which cause periodic sampling ofthe analog signal. The output of the sampling circuit is a series ofamplitude modulated pulses each having a duration equal to the durationof the sampling pulses and an amplitude equal to the amplitude of theanalog input wave'during each sampling period.

The sampling pulses are produced by a common low amplitude clock pulsesource and are amplified by a pulse amplifier circuit for application tothe sampling gate. Rise time or fall time distortion of the clock pulsewill be amplified by the pulse amplifier and will thereby affect therise and fall time of the PAM output from the sampling gate.Furthermore, the pulse amplifiers will tend to produce additionaldistortion of the clock timing pulses due to the effect of straycapacitance in the sampling gate on the rise and fall timesof thepulses.

In the prior art, timing pulses for a PAM sampling gate are suppliedthrough a common current-modeswitch acting as a pulse amplifier circuit.A channel timing pulse source is connected to the input of thecurrent-mode-switch which amplifies each timing pulse and applies it tothe input of the sampling gate. In general the gate input is inductivelycoupled to the output of the current-mode-switch through a pulsetransformer. The stray capacitance of the inductive pulse transformertends to round the leading edge of the pulses by creating long transientrise times which results in distortion of the PAM pulses produced by thesampling gate.

The current-mode-switch is a non-linear emitter coupled logic gate whichhas negative transient enhancement characteristics and is commonly usedas an amplifying circuit. These characteristics of thecurrentmode-switch provide a good fall time for a given input pulse,however, the switch is unable to compensate for the storage effect ofstray capacitance in an output circult.

It is an object of the invention to provide an improved pulse amplifierhaving a positive transient enhancement characteristic.

It is another object of the invention to provide a short rise time and ashort fall time at the output of a pulse amplifier circuit.

It is a further object of the invention to provide a squared pulse inputto a sampling gate in a digital transmission system.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating theinvention. FIG. 2 is a comparison of the amplified pulse waveform withand without the subject invention.

DETAILED DESCRIPTION OF THE INVENTION Referring now to FIG. 1 whereinthe schematic diagram of a preferred embodiment of the pulse amplifiercircuit according to the present invention is shown, an analog inputsignal which is typically audio information is impressed upon aconventional PAM sampler 1. The PAM sampler produces a series ofvariable amplitude pulses which together provide a discontinuousapproximation of the input analog signal in response to the samplingpulses from a pulse amplifier 2. A source of clock pulses 3 is connectedto the input of the pulse amplifier and supplies a train of samplingpulses having a low amplitude and a short duration. The pulses aresufiiciently spaced apart in time to allow the digitizing of each PAMoutput pulse. Each clock pulse is amplified by a current-mode-switchpulse amplifier 4 to a level which is sufficient to allow accuratesampling of the analog voice input signal by sampler 1.

The current-mode-switch is a non-linear, emitter coupled logic gatehaving a negative transient enhancement characteristic. Thecurrent-mode-switch has a polarity inversion characteristic and becauseof its enhancement properties will tend to provide a fast fall time fora positive input pulse as illustrated in FIG. 2.

The current-mode-switch shown in FIG. 1 consists of two transistors, TR,and TR, which have their emitters connected in common to source ofpotential -E,

through a resistor R,. By using a large negative voltage E, and a largeresistor R, such that any voltage excursion at point a becomes much lessthan the voltage -E,, the combination of R, and E, effectively becomes aconstant current. source. Therefore it is reasonable to assume thatcurrent is constantly being supplied to the emitters of transistors TR,and TR,.

Transistors TR, and TR, are current switches which mutually exclusivelytransmit current from their emitter to their collector terminals inresponse to the relative magnitude of input signals at the baseterminals of the two transistors. The flow of current through therespective transistors TR, or TR, will determine the magnitude of thevoltage at the output terminal of the current-mode-switch amplifier.Amplification of an input pulse is provided by properly biasing theoutput paths of transistors TR, and TR,. For the circuit shown in FIG.1, the bias voltage EC, is larger than the bias voltage EC,.

For purposes of this analysis we shall assume that all elements in thedisclosed circuit are silicon elements having a known voltage dropacross the diode junction of the N and P interface. However, it will beobvious to one of ordinary skill in the art that it is within the scopeof this invention to substitute other similar diode devices such asgermanium crystals which will also exhibit a known voltage drop acrossthe interface of the device.

The base of TR, is connected to a reference voltage which is shown asground in FIG. 1 but may be any referenced voltage having the properrelative value to the input voltages at TR,. The base of TR, isconnected as the input terminal of the current-mode-switch and receivesa train of pulses having peak and valley amplitudes which vary aroundthe DC. reference voltage applied to the base of TR,.

If we assume that the base of TR, is connected to ground and thatinitially TR, is conducting due to a low input of TR,, current will flowfrom the constant current source E, and R, through the emitter andcollector of TR, to the output of the transistor. The base to emittervoltage drop in transistor TR, will be the standard voltage drop acrossa silicon diode of approximately 0.7 volts causing the voltage at pointa to become O.7 volts. Since the input to TR, is low, that is, below thereference level of the base at TR,, the voltage drop from the base tothe emitter of TR, tending to forward bias the base to emitter diodewill be relatively small or even negative if the input signal issufficiently negative, Since a minimum forward bias is required to causeconduction, the small forward bias will be of insufficient magnitude toturn on the base to emitter diode and cause current to flow.

For a low input to TR,, the voltage at the collector of transistor TR,will be held at +EC, volts due to the current from bias voltage sourceEC,. The voltage at junction b will be equal to the bias voltage EC,plus one diode drop across RC,. The base of transistor TR, is directlyconnected to junction b and the emitter of TR;,, at the pulse amplifieroutput, will be at EC, volts due to the voltage drop across the base toemitter diode. Transistor TR which provides positive edge enhancement,also maintains the output voltage at EC, by passing current from E,whenever the output voltage falls below EC,. Since bias EC, is smallerthan bias EC,,

the magnitude of the voltage at the output reverse biases diode RC, andRC, and prevents any flow of current from bias +EC, to the output. Thus,for a low input to TR, the output of the current-mode-switch is invertedand is maintained at a high level by TR, until the input to TR, israised to a level which will turn TR, on and turn TR, off.

When the input pulse at the base of TR, goes high, the base to emitterdiode in transistor TR, becomes forward biased above its minimumthreshold voltage and begins to conduct current, thereby raising thevoltage at point a. The rapid rise in voltage at point a will tend toreduce the voltage drop across the base to emitter diode of transistorTR, below the minimum forward bias threshold and thereby cut offtransmission of current from the emitter to the collector of transistorTR,. During this high input, when the input to TR, is greater than thereference voltage at TR,, the current flows from the constant currentsource through TR, to the output of TR, and cannot flow through TR,.

The transfer of current flow from TR, to TR, occurs at high speed due tothe negative enhancement characteristics of the amplifier and causes thevoltage at junction b to drop rapidly from its original value of EC,+0.7 volts towards ground. As the voltage at b drops rapidly, thebase-emitter junction of TR, will become back biased and TR, will turnoff rapidly. However, the bias +EC, will tend to clamp the junction b toa value of +EC, 1.4 volts (diode drops across RC, and RC,) such that, asthe junction b tends to go below that value, bias voltage +EC, willsupply current to maintain the voltage at junction b constant. Nocurrent can flow through TR, and since +EC, is greater than +EC,, thediode RC, will be back biased and will not pass current.

Current will therefore flow to TR, from the bias +E,

through R,, from bias +EC, through RC, and RC, and from the load throughRC, to maintain the value of the voltage at the output terminal at +EC,minus one diode drop. The voltage drop across RC, will hold a back biason TR, and TR, will be non-conductive for low level output signals.

It can be seen that for a given magnitude of input voltage, current willflow through one transistor and not through the other transistor of thecurrent-modeswitch, while for a change in the magnitude of inputvoltage, current will switch its path to flow through the secondtransistor and not through the first transistor. Since the magnitude ofthe bias voltages +EC, and +EC, are greater than the magnitude of theinput pulse which is applied to the base of transistor TR,, andamplifying efiect is achieved.

The effect of stray capacitance at the output terminal may be seen byexamining the output voltages of the current mode switch amplifier asshown in FIG. 1. If the input is low and TR, is conducting, the outputvoltage will be at a high value of +EC,. The stray capacitance at theoutput terminal stores the voltage appearing at the output with a timeconstant which is dependent upon the values of the stray capacitance C,and the load resistance R,. This stored voltage will be maintained untilthe input to TR, is raised to a high level at which point the storedvoltage discharges through RC, and TR, and immediately causes the outputto drop to +EC, minus one diode drop volts. The output remains at thislow level for the high input to TR, until the application of another lowinput pulse to TR,.

In the prior art, when the input was high and became low, the outputvoltage of the current mode switch would rise to EC,. However, since thevoltage at the output to the current mode switch was low (approximatelyEC,) and the new value of voltage at the junction b is high(approximately EC,), the diode RC is back biased until the straycapacitance C, can be charged to the voltage equal to +EC, over a timeperiod dependent upon C, and R of the output circuits. The time taken tocharge the stray capacitance causes the rise time of the output pulse tobe delayed significantly, thereby rounding the corners of the resultingpulse and causing serious distortion in the output circuit as seen inFIG. 2.

The present invention solves the problem by providing a high source ofcurrent through TR to the output load. The current compensates the backbiasing of diode RC, by quickly supplying current to the straycapacitance and thereby reducing the rise time of the output voltage.Since the bias voltage +E is nearly an infinite source of current, anemitter follower transistor is connected as a switch between the voltagesource +5, and the output with its base connected to the junction b asshown in FIG. 1. Upon application of a proper signal to the base, it canbe seen that current will flow from the source of bias potential +Edirectly to the output through the collector and emitter terminals ofthe transistor TR When TR is turned on, voltage at junction b jumps from+EC to +EC,. This high voltage at the base of TR, causes TR, to turn onand connects +E to the output. The voltage at the output rises rapidlyuntil it reaches +EC, whereupon the base to emitter diode of TR becomesless forward biased and turns TR, off. The transistor remains in astandby state and conducts current to the output whenever the voltage atthe output drops below the voltage at junction b minus one diode drop.The present invention employs the emitter follower to rapidly supplycurrent to the output during the positive transient period of the outputpulse.

Once a high voltage is again impressed upon the transistor TR, thecurrent mode switch changes state causing the current of TR, to flow.The current through TR, is cut off and the stray capacitance voltage isdischarged through RC and TR,. The amplified output pulse will rapidlydrop to its low level in a short fall time and square the following edgeof the amplified pulse.

Although the invention has been disclosed as a pulse amplifier for a PAMsampler it would be obvious to one of ordinary skill in the art thatthis pulse amplifier may be used in any applications requiring highamplitude pulses having short rise and fall times.

I claim:

1. An improved pulse amplifier having an input terminal and an outputterminal and supplying a capacitive load comprising:

a. a logic gate connected to said input terminal including a firsttransistor emitter coupled to a second transistor,

b. a first voltage source connected to the output of said secondtransistor,

c. first diode means connected between said first voltage source and theoutput of said logic gate,

(1. a second voltage source having a voltage significantly less thansaid first voltage source,

e. second diode means connected between said second voltage source andsaid out ut terminal f. fl'lll'd diode means connected. be ween saidfirst diode means and said output terminal, said first transistor beingbiased so as to be rendered conductive by positive going pulses at saidinput terminal to cause said second and third diode means to conductthereby maintaining the voltage of said output terminal substantially atthe value of said second voltage source and said second transistor beingbiased so as to be rendered conductive by negative going pulses at said.input terminal to cause said first diode means to conduct and saidsecond and third diode means to cease conducting thereby maintaining thevoltage at said output terminal substantially at the value of said firstvoltage source,

g. current supply means, and

h. an emitter follower current switch connected between said currentsupply means and said output terminal, said switch being responsive to arise in voltage at the output of said logic gate to pass current fromsaid current source to said capacitive load thereby reducing the risetime of the output pulse.

2. The amplifier as claimed in claim 1 wherein said logic gate includesmeans to increase the fall time of said output pulse.

1. An improved pulse amplifier having an input terminal and an outputterminal and supplying a capacitive load comprising: a. a logic gateconnected to said input terminal including a first transistor emittercoupled to a second transistor, b. a first voltage source connected tothe output of said second transistor, c. first diode means connectedbetween said first voltage source and the output of said logic gate, d.a second voltage source having a voltage significantly less than saidfirst voltage source, e. second diode means connected between saidsecond voltage source and said output terminal, f. third diode meansconnected between said first diode means and said output terminal, saidfirst transistor being biased so as to be rendered conductive bypositive going pulses at said input terminal to cause said second andthird diode means to conduct thereby maintaining the voltage of saidoutput terminal substantially at the value of said second voltage sourceand said second transistor being biased so as to be rendered conductiveby negative going pulses at said input terminal to cause said firstdiode means to conduct and said second and third diode means to ceaseconducting thereby maintaining the voltage at said output terminalsubstantially at the value of said first voltage source, g. currentsupply means, and h. an emitter follower current switch connectedbetween said current supply means and said output terminal, said switchbeing responsive to a rise in voltage at the output of said logic gAteto pass current from said current source to said capacitive load therebyreducing the rise time of the output pulse.
 2. The amplifier as claimedin claim 1 wherein said logic gate includes means to increase the falltime of said output pulse.